[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #31 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Jacob Lifshay from comment #30)
> (In reply to Luke Kenneth Casson Leighton from comment #28)
> > (In reply to Jacob Lifshay from comment #23)
> > > scalar registers are a *totally different kind* of argument, they are *not
> > > vectors*, 
> > 
> > they are: look at the pseudocode.  they're "degenerate vectors of length
> > equal to one".

clarification: don't agree with this
> > 
> > i think what you might be imagining to be the case is, "if VL==1 && SUBVL==1
> > then SV is disabled, and a different codepath followed that goes exclusively
> > to a scalar-only OpenPOWER v3.0B compliant codepath"
> > 
> > this categorically and fundamentally is NOT the case.

agree that VL==1 && SUBVL ==1 being special is not the case.
> 
> yup, totally agreed.

-- 
You are receiving this mail because:
You are on the CC list for the bug.