[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #29 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #27)

> that depends on the instruction (icr if we added a signed/unsigned bit to
> svp64, we should).

tired.  brief.  considered it.  rejected it.  OpenPOWER has extsw.  therefore
conpilers spit out code that groks extsw.  vectorisation of that: dead
straightforward.

change to add s/u mode needs big RTL change, entire ALUs complete rewrite.
intrusive complier behavioural change.  not happy.  don't have time.  too big
change, too intrusive, throws away months of work. therefore, reject.

saturation on the other hand: s/u added.  why? because not included in
OpenPOWER scalar, therefore *we* define rules, and define them as a
post-processing phase just before CR testing.  not intrusive, incremental
change, works well.

-- 
You are receiving this mail because:
You are on the CC list for the bug.