[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #21 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #19)

> How about this:
> 
> we just define SV to trap when not in little-endian mode for now,

that punishes BE and makes it a second-rate citizen.

which in turn completely cuts us off from China, Japan and India Industrial
markets, where many Industrial Control Systems are still using VME Bus and
68000 family processors.

lhbrx.  vectorised.  data loaded in correc order.  solved.

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