[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)
> if the underlying SRAM of the regfile is treated as "a direct representation
> of memory" i will be LITERALLY unable to cope with the complexity introduced
> due to MASSIVE confusion as to what is now in which order.

How about this:

we just define SV to trap when not in little-endian mode for now, we can then
take our time to figure out which way the registers go in big endian mode and
implement it later.

Sound like a good idea?

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