[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Thu Dec 31 00:12:23 GMT 2020


--- Comment #19 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #16)
> if the underlying SRAM of the regfile is treated as "a direct representation
> of memory" i will be LITERALLY unable to cope with the complexity introduced
> due to MASSIVE confusion as to what is now in which order.

How about this:

we just define SV to trap when not in little-endian mode for now, we can then
take our time to figure out which way the registers go in big endian mode and
implement it later.

Sound like a good idea?

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list