[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #17 from Jacob Lifshay <programmerjake at gmail.com> ---
So, assuming r4==0x0102030405060708:
li r3, 5
setvli r0, 4
add r4.v, r3.s, r4.v, subvl=1, elwidth=8-bit

produces on little endian:
r4==0x010203040A0B0C0D

produces on big endian:
r4==0x0607080905060708

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