[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #11 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #8)
> basically, it will make the in-memory layout of vector types identical to
> the in-register layout.

which i already had such insane difficulty getting right that modifying it in
the least bit is categorically a bad idea.  i literally had to try all possible
permutations of byteswapping until the unit tests happened to pass.  i do not
wish to go through that again.

-- 
You are receiving this mail because:
You are on the CC list for the bug.