[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=560

--- Comment #9 from Jacob Lifshay <programmerjake at gmail.com> ---
I consider CRs weird enough (since they're rarely stored in memory) that they
shouldn't be used to decide our in-register layout of vector types, instead, we
should strive for consistency between registers and memory, since that makes a
bitcast, which is commonly assumed to be zero-cost, actually be zero cost.

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