[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Dec 30 22:23:41 GMT 2020


--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---



CRs (which caused merry hell to implement) being the guide here, i am very
reticent to go down this route, not least because of the time pressure that we
are under.

what i am inclined to suggest here is that any kind of in-register byteswapping
be performed explicitly by using bitmanip operations.  i started adding some of
those at the sv/bitmanip page.

the issue is that we didn't think of this 6-12 months ago, it's only just come
up, and there's no spare encoding space.

effectively, considering the regfiles as an SRAM and allowing the data within
them to be either LE or BE encoded is something that needs its own dedicated
MSR bit.

it's just not "normal practice", plus, to be honest, LDST already has LE/BE and
byte-reverse.  if you really want the data in the registers to be inverted,
call the bitmanip byte-reverse opcode or push the data out through memory and

on balance i am very much disinclined to add this in any way, unless there is a
seriously compelling use-case.

You are receiving this mail because:
You are on the CC list for the bug.

More information about the Libre-SOC-ISA mailing list