[Libre-soc-isa] [Bug 560] big-endian little-endian SV regfile layout idea

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Dec 30 20:00:38 GMT 2020


Alexandre Oliva <oliva at libre-soc.org> changed:

           What    |Removed                     |Added
                 CC|                            |oliva at libre-soc.org

--- Comment #3 from Alexandre Oliva <oliva at libre-soc.org> ---
comment 2 is unrelated and was covered in the call: it was just noise from
earlier requirements on compressed instructions, that our decoder had to map
things to preexisting ppc insns.  this is not the case of the svp64 loop

as for endianness of vectors, I think an important property to strive for is
for the first element of a vector, when the register is used as a vector, to
match the scalar version of the same register, when it's used as scalar,
regardless of endianness.  things could get very confusing otherwise.

I imagine there may be reasons to do otherwise.  I haven't thought it through.

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