[Libre-soc-isa] [Bug 563] New: 128-bit instructions and SimpleV

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Wed Dec 30 19:27:26 GMT 2020


            Bug ID: 563
           Summary: 128-bit instructions and SimpleV
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: Other
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: programmerjake at gmail.com
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

I think we should support 128-bit elements symmetrically to 64/32/16/8-bit
operations by just having the 128-bit vsx instruction be the base instruction
that gets prefixed, this would mean subvl=1 has 128-bit subvectors, subvl=2 has
256-bit subvectors, 3 for 384-bit, and 4 for 512-bit.

this is because it doesn't make sense to have an instruction for a 64-bit half
of a intrinsically 128-bit operation such as f128 add.

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