[Libre-soc-isa] [Bug 559] analyse implications of automatic detection of changing VL loop direction

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=559

--- Comment #8 from Alexandre Oliva <oliva at libre-soc.org> ---
Indeed, automatic detection and reversal of direction won't do in general case.

We could still state that the insn operands must be such that there aren't
overlaps between inputs and outputs that could lead sequential operation to
behave differently from fully parallel operation, leaving those cases reserved
(meant to be unused) rather than defined in a way that is at odds with the
behavior and expectations of every other vector/simd processor out there. 
(hyperbole alert; I don't know them all ;-)

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