[Libre-soc-isa] [Bug 552] single-predication has "splat" capability, needs review

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=552

--- Comment #6 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
so i don't know if you recall the first discussion when i came up with the
cyclic shift register idea.  a conveyor belt attached between the regfiles and
CompUnis, both read and write, which have on each a piece of "state" which is
the difference between the port number on the regfile and the operand number on
the CompUnit.

each shift reduces that state by one, when it reaches zero the value is
"delivered".  what is nice is: if there are not enough free write ports the
result keeps cycling until one *is* available.  also this same trick can be
used for operand forwarding (including to multiple units).

this is all on the scalar side: the vector side if kept simple should not need
it, and the Monster FSM has its own SR.

here's the thing: one-to-many delivery *might* and i stress might - be possible
to jam in to the cyclic register system as part of Operand Forwarding.

however to keep the design from going completely insane it really does need the
micro-coding, splitting out the generation of the scalar op from the broadcast
copy/mv.

and, if done properly, the OoO Engine should sort things out as far as
parallelism is concerned.

certainly if the number of vsplat dest-writes exceeds the number of regfile
ports nothing is going to help get good performance except if by chance operand
forwarding kicks in.

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