[Libre-soc-isa] [Bug 552] single-predication has "splat" capability, needs review

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=552

--- Comment #3 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #2)
> Note that splat will be very common in graphics code (I'd randomly guess
> 10-20% of instructions, though a lot of those can be done by having a scalar
> source on a vector op), so we will probably want to take the approach where
> we have the one scalar ALU and just write to multiple destination registers.

this was the bit which was the "pain".  effectively that's a micro-coded op,
separating out the actual scalar operation from the "copy-to-multiple".

which starts to get us into CISC territory as far as implementation is
concerned.

let me think it through...

* result is produced
* then written to first dest (including CR)
* then a micro op "copy" splats it out (predicated).  including CR, here
(arrrg)

if that is interrupted, it can be resumed at the copy phase as long as you can
determine that the result was written.

that's going to be a pig, but it's doable.

spec updated btw.

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