[Libre-soc-isa] [Bug 535] setvl/setvli encoding & future reg file expansion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=535

--- Comment #20 from Jacob Lifshay <programmerjake at gmail.com> ---
(In reply to Luke Kenneth Casson Leighton from comment #19)
> (In reply to Luke Kenneth Casson Leighton from comment #18)
> > jacob says VL should be allowed to be set to zero because
> > then you can have a CR branch-condition test.
> 
> right: ok, so this is possible: VL can indeed be set to zero.  if the source
> register RA contains zero, VL will be set to zero.  then, when that happens
> (as long as you used "setvl." i.e. Rc=1 mode) the CR will indeed be set so
> that its eq-to-zero flag will be raised.

sounds good!

> 
> however setting the *immediate* it makes no sense to me for setvli to be
> able to set VL to zero.

yup, the field being zero can instead mean VL=64

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