[Libre-soc-isa] [Bug 544] New: assessment of OpenPOWER SIMD instructions (misnamed "vector")

bugzilla-daemon at libre-soc.org bugzilla-daemon at libre-soc.org
Tue Dec 8 12:54:35 GMT 2020


            Bug ID: 544
           Summary: assessment of OpenPOWER SIMD instructions (misnamed
           Product: Libre-SOC's first SoC
           Version: unspecified
          Hardware: PC
                OS: Linux
            Status: CONFIRMED
          Severity: enhancement
          Priority: ---
         Component: Specification
          Assignee: lkcl at lkcl.net
          Reporter: lkcl at lkcl.net
                CC: libre-soc-isa at lists.libre-soc.org
   NLnet milestone: ---

an examination of the OpenPOWER SIMD instructions is needed.  it cannot
strictly be called "Vector" because vectors are variable-length, where
VSX is fixed-length (i.e. SIMD).

preliminary investigation shows the inclusion of:

* DSP-style integer clamp/saturate operations
* pixel-style data reordering (in and out of 16 RGB and 32-bit formats)
* a very good type of rotate that reads a mask from part of a register
* min/max selection on both integer and FP
* FP estimation functions (log, exp, recp, rsqrt)
* Rijndael FIPS-197 and SHA-256/512 primitives
* there are some bitmanip operations that also seem not to be
  vector operations, but are more along the lines of taking advantage
  of the fact that the VSX registers are 128 bit

analysis of these instructions is valuable with a view to guiding whether
and how they should be included in Simple-V

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