[Libre-soc-isa] [Bug 535] setvl/setvli encoding & future reg file expansion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=535

--- Comment #12 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
(In reply to Jacob Lifshay from comment #11)

> > > For setvli, since the value VL is set to is a constant, having a destination
> > > register is much less important.

> your talking about setvl, not setvli. setvli sets both VL and MVL to a known
> constant for use with fixed-length vectors, no need to loop.

ohh yepyep got it.

ok, i know what happened.  the instruction as designed (and pseudocode) is a
hybrid all-in-one, where setvli effectively becomes a pseudo-op not a real op.

so i misunderstood, with setvl being synonymous with setvli.

my feeling is, it's not worth having separate setvl and setvli instructions,
such that setvli not having a dest reg is moot.

in *compressed*, do we want a separate setvli? mmm... maayyybeee... although i
don't think there's space.


(In reply to Jacob Lifshay from comment #11)

> > > We can even include setting CR0 (if Rc = 1) to allow jumps on VL == 0
> > > immediately after setvl.
> > 
> > awesome, isn't it? :)  i love CRs.  see comment #4 i put Rc support in.  i
> > mean, it's part of XO-form so why not.
> 
> yup, that's what I was referencing.

ok,ok, this is hilarious: if we allow setvl to be an SV-P48 prefixable
instruction, it *might* be possible (stress: might) to get CR0 retargetted at
an alternative CR.

one downside of Rc=1 is you can't doecify an alternative CR, end result you
have to move it to another CR then the bc can use that alternative target.

but... if SV-P48 can set the alternative to CR0 the extra instruction is saved.

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