[Libre-soc-isa] [Bug 535] setvl/setvli encoding & future reg file expansion

[bugzilla-daemon at libre-soc.org]

https://bugs.libre-soc.org/show_bug.cgi?id=535

--- Comment #1 from Luke Kenneth Casson Leighton <lkcl at lkcl.net> ---
XFX-Form with a single XO, and RT allocated to the register to be set
RT=min(MVL, min(RT, VL)), there are 10 remaining bits to use to select VL, MVL,
and still have space for expansion.  this without compromising on encoding
space for MVL, assuming it's ok to have a bit that specifies to set MVL and VL
at the same time.  OE=1 (bit 31) can be used to indicate "future encoding"

   bits 0:5   major op
   bits 6:10  (RT|0)
   bits 11:16 immed
   bit  17    set MVL to immed
   bit  18    set VL to immed
   bit  19:20 reserved
   bit  21:30 XO
   bit  31    reserved

totals 3 spare bits for future.

interesting thing about when bit 17 and 18 are zero, RT is set to VL (actually
min(min(RT, VL), MVL)) but without first setting VL to the immediate.

recommend also having (RT|0) to indicate that VL is to be set (and MVL) but RT
is not.

quite a bit of pseudocode but point is there is neither pressure to compromise
on encoding space or reserved space.

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