[Libre-soc-dev] Vertical-First mode with predicates

[Jacob Lifshay]

On Fri, Jun 17, 2022, 13:24 lkcl via Libre-soc-dev <
libre-soc-dev at lists.libre-soc.org> wrote:

> https://bugs.libre-soc.org/show_bug.cgi?id=862

...

> setvl VF=1
> loop:
> ld r3 # get predicate
> sv.addi/m=r3 r8.v, r8.v, 1
> addi r3, r3, 5
> sv.addi/m=r3 r8.v, r8.v, 1
> svstep.
> bnz loop
>
> at which point the hardware melts from overload on the dual role.
>

imho it's fine, all you need is each sv.addi to read the value of r3 in
program order, both the ld and addi should compute the same values every
loop iteration.

e.g. assuming each loop processes 4 elements:
instruction sequence (using lsb0 bit numbering):
vstart = 0
VL = 8
r8-15 = 0
ld r3 # get predicate, assume it's 0xAA
r3 = 0xAA
sv.addi/m=r3 r8.v, r8.v, 1
r8-11 = [0, 1, 0, 1] because of predicate bits 0-3
addi r3, r3, 5
r3 = 0xAF
sv.addi/m=r3 r8.v, r8.v, 1
r8-11 = [1, 2, 1, 2] because of predicate bits 0-3
svstep.
vstart = 4
bnz loop
ld r3 # get predicate, assume it's 0xAA
r3 = 0xAA
sv.addi/m=r3 r8.v, r8.v, 1
r12-15 = [0, 1, 0, 1] because of predicate bits 4-7
addi r3, r3, 5
r3 = 0xAF
sv.addi/m=r3 r8.v, r8.v, 1
r12-15 = [0, 2, 0, 2] because of predicate bits 4-7
svstep.
vstart = 0
bnz loop

Jacob