[Libre-soc-dev] mv.zip and mv.unzip (vector pack and unpack)

[lkcl]

sorry using annoying mailer.  sz/dz apply at the sm/dm VL-for-loop level.

for i in range(VL)
    if not predicate[i] continue
       for j in range(SUBVL)

so mentioning them is a red herring, sorry.

i'm good with swizzle=0 being 0/1.0 and swizzle=1 being sat-max/satu-max

skip and 0/1 are both achievable

the formerly-reserved encoding 0b001 is used to mark the dest-end vector length, if it is not included then the dest subvl is assumed to be vec4.

in this way you can select any-len to any-len, i am just trying to write the pseudocode, now.  pack/unpack makes it... particularly obtuse.




On June 13, 2022 5:56:24 PM GMT+01:00, Jacob Lifshay <programmerjake at gmail.com> wrote:
>On Mon, Jun 13, 2022, 09:50 lkcl <luke.leighton at gmail.com> wrote:
>
>> love the override meaning of Saturation signed/unsigned to give more
>> constants. put it in the page.
>>
>> can't do 0 -max +max in the same instruction, annoyingly, unless
>using
>> zeroing predication hmm i am getting brainmeltdown thinking of how
>that
>> would work, urr there is both sz and dz.
>>
>
>-max isn't commonly used so can be left out.
>
>>
>> nornal mode: https://libre-soc.org/openpower/sv/normal/
>>
>> 10 N dz sz sat mode: N=0/1 u/s
>>
>> if dz is set then zeros would be inserted on swizzle-skipped
>elements, but
>> the sat/u would remain... no, too complicated.
>>
>> two mv instructions it'll have to be, one for zeros, the other for
>sat/u.
>>
>
>we likely need skip and 0/1 in the same instruction, so they can be
>done
>simultaneously. so, no, dz won't be what's needed.
>
>>
>> skipping is COMPLEX it basically means a static predicate mask
>built-in to
>> the swizzle, but the implication is that the source subvec len is
>> *different* from the dest,
>>
>
>source subvec len being different from the dest subvec len is a large
>part
>of why mv.swizzle exists, it is very much needed.
>
>Jacob
>
>>