[Libre-soc-dev] svp64 review and "FlexiVec" alternative

[Jacob Lifshay]

On Tue, Jul 26, 2022, 17:11 Jacob Bachmeyer via Libre-soc-dev <
libre-soc-dev at lists.libre-soc.org> wrote:

> Which means that Simple-V may not be a suitable fit for Power ISA any
> more than it fit in RISC-V.


SimpleV works just fine in RISC-V, the reason we switched to Power is
because of other factors, such as the OpenPower Foundation being much more
inclined to work with us.

  OpenSPARC


that's not a particularly high register count...you can still only access
64 registers at any one time, 32 int, 32 fp. All of the additional
registers used for the call stack are usually inaccessible. SimpleV
currently has >4x as many registers accessible (128 int, 128 fp, 128 cr
fields) and that will likely increase in the future.

or another high-register-count
> ISA might be useful, or possibly a dedicated Libre-SOC GPU architecture,
> with an OpenPOWER (sans vector facilities) control unit in the actual SOC.
>

i think we should specifically have the same ISA for cpu and gpu stuff, it
makes possible optimizing 3D graphics much more if it becomes wide-spread,
as opposed to current GPUs where the vendors basically forbid you from
using their native ISA and insist you must use their compiler to process
all your gpu code first. Using the same ISA also reduces communication
overhead because you can just treat it as a normal multithreaded program,
rather than this thing that you have to go to great effort to queue up work
for and use special kernel drivers, etc.

Jacob