[Libre-soc-dev] svp64 review
jcb62281 at gmail.com
Tue Jul 26 02:53:36 BST 2022
Luke Kenneth Casson Leighton wrote:
> crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68
> On Mon, Jul 25, 2022 at 6:22 AM Jacob Bachmeyer via Libre-soc-dev
> <libre-soc-dev at lists.libre-soc.org> wrote:
>>> in other words, i took the concept of "Sub-PC" very seriously and
>>> treated it literally as part of the [absolutely] critical Context, aka
>>> a peer of PC and MSR.
>> If nested traps are possible, the trap handler still must preserve
>> SVSRR1 somewhere.
> i missed this earlier - yes, due to the strict rules surrounding
> keeping SVSTATE up-to-date and precise-interruptible, it's
> even possible to perform function calls within those Vertical-First
> this is what the (new) SVLR is for: to save SVSTATE into SVLR
> at *exactly* the same time as PC is stored into LR.
> the caveat on that one though is that if the function call is using
> REMAP at the time, the REMAP SPRs have to be explicitly
> saved/restored. there's 4 of them so it's a bit much to have
> SVLRSHAPE0-3 as well.
> given that read/write of SVLR has to be added to the branch pipeline,
> we can get away with adding one more SPR to the branch
> pipeline but not five.
When a trap is taken (so we have gone from user mode ("problem state" in
the Power ISA spec) to some privileged mode) what happens? Those are
the handlers I am talking about -- system software will need to
save/restore the additional state somewhere.
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