[Libre-soc-dev] daily kan-ban update 03jul2022

[Tobias Platen]

On Mon, 2022-07-04 at 19:02 -0300, Cesar Strauss via Libre-soc-dev
wrote:
> Em 03/07/2022 15:49, Tobias Platen via Libre-soc-dev escreveu:
> > orangecrab
> > WERROR: Failed to find a route for arc 2 of net
> > ddrphy_ddr3_0__a__o_fclk.
> 
> 
> For Versa, which routes successfully, I see in top.tim:
> 
> Info: Promoted 'ddrphy_ddr3_0__a__o_fclk' to bank 6 ECLK0.
> Info: Promoted 'ddrphy_ddr3_0__a__o_fclk' to bank 7 ECLK0.
> 
> For OrangeCrab, I see instead:
> 
> Info: Promoted 'ddrphy_ddr3_0__a__o_fclk' to bank 7 ECLK0.
> Info: Promoted 'ddrphy_ddr3_0__a__o_fclk' to bank 6 ECLK0.
> Info: Promoted 'ddrphy_ddr3_0__a__o_fclk' to bank 2 ECLK0.
> 
> ... which looks suspicious. Maybe the extra clock buffer is needed on
> the OrangeCrab, due to its particular assignment of DRAM pins to
> banks.
> 
> LiteX does seem able to build designs for the OrangeCrab, including 
> DRAM3. It outputs:
> 
> Info: Promoted 'sys2x_clk' to bank 7 ECLK1.
> Info: Promoted 'sys2x_clk' to bank 6 ECLK1.
> Info: Promoted 'sys2x_clk' to bank 2 ECLK1.
> 
> Maybe some attribute is missing, on the ls2 clock generator, or the
> PLL. 
> I'll compare with LiteX / LiteDRAM, and see if I can spot the
> difference.
> 
> Regards,
> 
> Cesar
> 
I'll have a look at that this evening.
> 
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