[Libre-soc-dev] setvl lost its reserved fields (was: setvl gaining CTR mode)

[Jacob Lifshay]

On Sat, Jul 2, 2022, 12:01 Luke Kenneth Casson Leighton via Libre-soc-dev <
libre-soc-dev at lists.libre-soc.org> wrote:
> if it wasn't for bc having a CTR-dec mode this would not be worth it.
> sv.bc has the abiltiy to decrement CTR in various ways, so it was
> quite important to also make it possible for VL to be set based on
> CTR.
>
> thoughts appreciated

seems fine to me.

though I just now noticed that at some point setvl lost the reserved bits
which we need to allow enabling future extensions to svp64, such as more
registers and/or 128-bit registers (lets just assume we want space for
future extensions and lets not argue about 128-bit registers right now)...

since the SVi field is 7 bits currently (assuming I calculated correctly)
and we only need 6 bits for that (2^6 values -- 1 to 64, encoded as 0-63),
imho we should split one bit out to be reserved for enabling future
extensions.

Imho we should reserve more than one bit for future extensions so we can
support more than just one extension.

We can take more bits from XO -- or merge or just plain remove the `ms` and
`vs` bits (since imho mfspr is sufficient for getvl and being able to
independently set VL and MVL isn't useful (MVL itself as a separate
register is redundant imho -- the compiler should always know the exact
value of MVL -- it allocated the registers vectors are stored in after
all)).

that would leave the following setvl modes (ignoring Rc and vf for brevity
-- they haven't been removed):
getvl would be mfspr rt, VL

setvl rt, ra, imm
    mvl = imm
    rt = vl = min(ra, imm)

setvl rt, 0, imm
    mvl = imm
    rt = vl = min(ctr, imm)

setvl 0, ra, imm
    mvl = imm
    vl = min(ra, imm)

setvl 0, 0, imm
    mvl = vl = imm

notice how mvl isn't ever read? imho it can/should just be deleted.

Jacob