[Libre-soc-dev] SimdSignal library

[Jacob Lifshay]

I decided that I think it is still a better idea to have a
PartitionedSignal equivalent that supports arbitrary lane sizes, even
if they need padding. I also think that trying to force Simd-ness apon
nmigen's Module, If, Cat, Mux, Switch, and Value is not a good idea
primarily because of confusion, and also because creating a hard fork
of nmigen is not a good idea. Therefore, I ended up creating a
proof-of-concept SimdSignal library that is all laid out with the API
I think is best:

https://salsa.debian.org/Kazan-team/simd_signal/-/tree/master

I got a little carried away with the implementation, I had been
planning on working on it a day or two before posting on the mailing
list rather than a week...oops.

Fully implemented and tested:
I implemented SimdPartMode, which is a replacement for PartitionPoints
that instead operates on abstract-sized "parts", where an aligned
power-of-two-sized group of "parts" forms a SimdLane. See the docs of
SimdPartMode for more details, along with validity constraints.
There is also SimdLayout, that has all the logic for calculating where
lanes go and how much padding is needed.


Fully implemented (except for testing):
SimdCat: equivalent to Cat
SimdRepl: equivalent to Repl
SimdConvertLayout:
    SimdValue that converts layouts: truncating, sign-extending, or
    zero-extending as needed. It can also fill padding with known bits.
SimdLaneSizeLookupValue:
    SimdValue where each lane is set to a nmigen Value that is looked-up
    based on the lane's size in parts
SimdBoolCast: used to implement SimdValue.bool()
SimdSignal: equivalent of Signal
SimdAssign:
    equivalent of Signal.eq(Value), already does all the hard parts
    (except for the handling needed for being nested inside conditionals)
SimdValueLaneSizewise: (abstract class)
    SimdValue that operates on a full-width value for each lane-size
    individually, then merges them all to create the final output.
SimdValueLanewise: (abstract class)
    SimdValue that operates on each lane individually, then merges them
    all to create the final output


Partially implemented:
SimdValue:
    mostly just missing __add__ and similar methods, the core
    functionality is implemented
SimdModule:
    parsing the AST for statements (assignments, If, Elif, Else,
    Switch, Case, Default) is supported, generating the corresponding
    nmigen isn't yet

Jacob