[Libre-soc-dev] adding PartitionedSignal support to nmigen's If/Switch/Case

[lkcl]

On September 22, 2021 1:42:21 AM UTC, Jacob Lifshay <programmerjake at gmail.com> wrote:

>Ok, I can work on implementing this...

cool.

here's where we got up to:

https://git.libre-soc.org/?p=ieee754fpu.git;a=blob;f=src/ieee754/part/partsig.py;h=f09b972a4c93e3a07e1f869c1f9a8ff16952743a;hb=c62fa3a7ee95832587d7725729dcdb9a002ae015#l236

eq, gt, le, lt, ne, all there (further up you can see add, sub, and, or, xor, and my favourite, shift. that one was.. hairy. 3 weeks to work through the logic alone)

PartitionedSignal works by creating modules behind the scenes, connecting up inputs and outputs so that as far as the user is concerned, they just did "a + b" or "a > b" and it "works" as expected, no matter the partition bits.  8-24-16-8-8 is perfectly acceptable, amazingly.

last i checked even the graphviz was readable because you get a PartitionedAdd module created, connected up, and apart from all the arrows going into the LHS rather than the output arrow being on the RHS  like it is with a standard Signal "+" graphviz representation it's still obvious what the functionality is.

missing things are the "big" ones, mul, div, mod, we can look at those later.  __mul__ will need to instantiate the PartitionedMul.  at which point all HDL Simulations become 10x slower so we have to be careful there.

the main priority blocker is m.If/Else.  once we have that it becomes possible to look at converting one of the simpler pipelines.

l.