[Libre-soc-dev] adding PartitionedSignal support to nmigen's If/Switch/Case

[Jacob Lifshay]

On Tue, Sep 21, 2021, 12:50 Jacob Lifshay <programmerjake at gmail.com> wrote:

> Generating a bunch of Ifs, one for each maximally-partitioned
> PartitionedSignal lane will theoretically work for If, though it will be
> incredibly inefficient and i don't think yosys will have an easy time
> optimizing it back to sane levels. There is also the problem that all code
> inside the If will still need to be vectorized (not a simple
> process)...essentially ending up with a very similar problem to the
> original idea of just reimplementing yosys's process passes.
> essentially...we will need to have the same
> vectorization/control-flow-into-data-flow-conversion code, the code just
> has a slightly different output format.
>

additional info on #nmigen:
https://libera.irclog.whitequark.org/nmigen/2021-09-21#30874521
<lkcl> a careful but mind-bending analysis (and associated actual
experiments and unit tests) should show and confirm that a simple
independent per-SIMD-partition *duplication* of the IR switch cases (each
one of which receives *one* bit from each of the cases), should be
perfectly sufficient
20:17 <programmerjake> unfortunately, just duplicating the If statement
bodies isn't sufficient, since you'd end up overwriting whole Signals
assigned to inside the bodies rather than just the lane desired
20:19 <programmerjake> therefore a whole body transformation is required,
which is essentially as complex and does much the same things as the
originally proposed vectorization/duplicating-yosys-process-passes

Jacob

>