[Libre-soc-dev] in-order core hazard detection working

[Luke Kenneth Casson Leighton]

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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68

On Tue, Nov 23, 2021 at 2:37 PM Luke Kenneth Casson Leighton
<lkcl at lkcl.net> wrote:

> yes, this is how the microwatt 0.bin 1.bin 2.bin etc. tests were created,
> Anton found (or wrote) a random-power-isa-instruction-generator
> i used these programs in the original side-by-side comparisons
> of microwatt-libresoc, last year.

https://git.libre-soc.org/?p=libresoc-litex.git;a=blob;f=sim.py;h=550339e46a22169fe19510da5d3032202f3f8aec;hb=b55917aafa6bbc9f16e1d97dc095e929c31aa81a#l298

single-stepping each instruction, waiting for completion, via the DMI interface,
then performing a full enumeration of all registers, and $display printing
them out.

swap out libre-soc for microwatt, repeat.  "diff -u" shows discrepancies.

l.