[Libre-soc-dev] Greetings

[lkcl]

On November 20, 2021 3:14:30 PM UTC, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:
>
>Hello Mitch,
>
>As Luke said, I'm now back from a short vacation. And I'm the
>main contact for the P&R and extraction, but my colleague
>Marie-Minerve is also heavily involved.
>
>
>On Fri, 2021-11-19 at 15:17 +0900, D. Mitch Bailey wrote:
>> Greetings,
>> 
>> Joining the mailing list after watching Jean-Paul Chaput's and Luke 
>> Leighton's presentations at Matt Venn's Opentapeout conference.
>> 
>> I'm a backend layout verification/EDA developer familiar with Cadence
>
>> and Calibre. I've also written an open-source program that has some
>of 
>> the capabilities of Calibre-PERC (I call it CVC - Circuit Validity 
>> Checker, but unfortunately there seems to be a verilog simulator
>that's 
>> also called CVC.). It detects static shorts, possible forward biased 
>> diodes and mosfet bulk connections, Hi-Z inputs (including outputs
>from 
>> cutoff regions), incorrect gate voltages for multipower designs, EOS 
>> (electrical overstress) errors, and a few others.
>
>  That would be very useful.

what do you think, should we include integration with this is the new NLnet Grant?

Mitch, would you be interested to receive some donations from NLnet to cover the integration: documentation, automated script to build the tool, cover discussion with LIP6 Engineers on how to do the integration itself, etc etc.

basically we don't "sponge" off of Libre Engineers time, we actively want to encourage it and pay for it.

given that what you have done involves verification, it is very easy to justify under the NGI Assure Programme, which this NLnet Grant is part of.
>  * The netlists instanciating standard cells gates *do not*
>    respect the interface ordering. This is a missing feature that
>    will be added in the upcoming monts to Coriolis (read the
>    spice netlists of the gates to know their order).
>      For TSMC we had to "instert" a intermediate spice level
>    just to reorder them. Necessary but very tedious work.
>
>  * In the sxlib version of Libre-SOC, you will still lack the
>    transistor level netlists of the SRAM blocks and PLL.
>      So you may not be able to check thoses parts.

a way round that is to compile a special version which simply doesn't have them.

>  In Alliance/Coriolis toolchain *in real mode* we still have
>  a missing link, the layout extractor. I think OpenROAD has
>  a gate level one, but we would like a transistor-level one.
>  I everything goes according to plan, we will be starting
>  the development of one next year, with very basic features.

i remembered we have the meeting on Tuesday, so i created a toplevel Milestone bugreport.

https://bugs.libre-soc.org/show_bug.cgi?id=748

we should fill in at least the toplevel tasks and put some idea of timescales.  remember that work done prior to Nov 16th (appx when the Grant was approved) cannot receive donations but anything after that, as long as it has a Milestone, can be.

Mitch if you would like the LVS Checker integration to be part of that please let me know i will create a bugzilla acct for you.

l.