[Libre-soc-dev] ReservationStations2

[lkcl]

works great.
https://git.libre-soc.org/?p=nmutil.git;a=blob;f=src/nmutil/concurrentunit.py;hb=HEAD

it effectively presents the exact same ready/valid signalling of the underlying ALU, making it look as if there are multiple identical ALUs but in fact there is only the one.  this allows "hazard tracking".

in theory it could be used for many other purposes, such as routing data through other types of single-resource objects: FIFOs, management of Buses, access to caches, and so on.

all the (relevant) FunctionUnits (ALU, Logical, Mul, CR, Shift) have been converted to RS form, currently with only one RS (num_rows=1) and test_issuer.py works fine.

a couple of things transpired:

* there was a bug in MultiCompUnit with respect to write masks.

the wrmask is an OR of the ALU "data ok" signals which should only be latched and listened to when ready/valid signalling is raised.

due to overzealous introduction of wrmask, wrmask (actually the "data ok" signals) had to be permanently left HI. that's now fixed.

* ReservationStations2 assumed a combinatorial setting of data (including ok signals) and valid strobe.

this was why the wrmask bug was found.  FunctionUnitSingle used sync and left data.ok permanently HI.


the first version of RS2 was a 4-phase FSM.

* is input data ready, if so latch it
* is the ALU ready to accept, if so send it
* is the ALU output ready, if so latch in output RS
* is the output RS ready, is so deliver it.

this is horribly inefficient, introducing a 4-cycle delay on all ALU processing.  a simple change in the FSM allowed this to become 2 cycles and also not have any delays introduced by the RSes themselves: delivery and extraction is combinatorial:

* is the data ready AND is the ALU ready, if so send
* is the ALU output ready AND the output RS ready, if so deliver.

where the 2nd condition is not true then latching occurs and the old 4-phase FSM kicks back in.


what we now have is already active (added in fu/compunits.py), and can be used in both an InOrder and OutOfOrder core.  to all intents and purposes there are sort-of multiple ALUs all with the same ready/valid Signalling.

l.