[Libre-soc-dev] NGI POINTER gigabit ethernet router ASIC roadmap

[lkcl]

On November 1, 2021 11:42:09 AM UTC, Jean-Paul Chaput <Jean-Paul.Chaput at lip6.fr> wrote:

>Yes. It's floorplaning work. About the placement of SRAM (or *any*
>sizeable
>macro-block), they must be put on *any* side of the chip so the regular
>clock
>  tree spreading from the center of the design is not hampered.

interesting.
>I would like to start that exploratory work as soon as possible and not
>wait for a provisional realistic HDL to be ready. So would it be
>possible
>to have the size & numbers of macro-blocks (both SRAM & analogs) so I
>can
>create abstracts, and a "fake" design that instantiate them and has a
>similar
>  number of gates after logical synthesis? 

in theory we can use ls180 but instead of DFFs use SRAMs, some of them are binary-addressed, this will be easy.

however some regfiles are *unary* addressed (CR file) i.e. there is no binary-decoder needed as part of the SRAM.

but this should not affect what you want to do.

an option to ls180 to build with the regfile memories as a "blackbox" cell, this should work perfectly fine and give something of big size to use.

l.