[Libre-soc-dev] mmu unit test

[Luke Kenneth Casson Leighton]

tobias, i just saw the mmu rom unit test, it looks great, and i'm
astounded and delighted it works.

just fyi i removed a huge amount of code duplication, we really can't
afford to do that, as things will get quickly out of hand.

instead i did this, which seems to be all the modifications needed.
with that defaulting to None, there's "zero impact" on the other unit
tests, so it's all good.

just also did a couple of other updates.

btw just remember that ISACaller doesn't have RADIX MMU in it yet, and
doesn't recognise PRTBL etc. etc. so tests are not going to give the
right answers if you run with virtual memory enabled.  we need to fix
that.

l.


--- a/src/soc/simple/test/test_runner.py
+++ b/src/soc/simple/test/test_runner.py
@@ -119,10 +119,11 @@ def get_dmi(dmi, addr):


 class TestRunner(FHDLTestCase):
-    def __init__(self, tst_data, microwatt_mmu=False):
+    def __init__(self, tst_data, microwatt_mmu=False, rom=None):
         super().__init__("run_all")
         self.test_data = tst_data
         self.microwatt_mmu = microwatt_mmu
+        self.rom = None

     def run_all(self):
         m = Module()
@@ -392,6 +393,15 @@ class TestRunner(FHDLTestCase):
                    "issuer_simulator.vcd",
                    traces, styles, module='top.issuer')

+        # add run of instructions
         sim.add_sync_process(process)
+
+        # optionally, if a wishbone-based ROM is passed in, run that as an
+        # extra emulated process
+        if self.rom is not None:
+            dcache = core.fus.fus["mmu0"].alu.dcache
+            default_mem = self.rom
+            sim.add_sync_process(wrap(wb_get(dcache, default_mem, "DCACHE")))
+
         with sim.write_vcd("issuer_simulator.vcd"):
             sim.run()

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