[Libre-soc-dev] daily kan-ban update 17feb2021

[Tobias Platen]

Verified that running ld/st instructions drives the TestMemory on wishbone bus
of the dcache. Next step is filling the wishbone memory with a pagetable, and
verify address translation, both sucessfull read/write and exceptions.
Exceptions can change SPRs, that is not yet implemented.

-- 
Tobias Platen <libre-soc[at]platen-software[dot]de>