[Libre-soc-dev] first SVP64 Vector Sub-PC for-loop operational in python-based simulator

[Luke Kenneth Casson Leighton]

https://git.libre-soc.org/?p=soc.git;a=commitdiff;h=9078b2935beb4ba89dcd2af91bb5e3a0bcffbe71

the Finite State Machine which interacts through a new SPR, SVSTATE,
is operational and has 3 out of 8 required unit tests to demonstrate
at least the principle:

* all vector (RT, RA, RB)
* RT=scalar, RA/RB=vector
* RT=vector, RA=scalar, RB=vector

there's 3 registers so there are *eight* actual combinations.  the
number of unit tests - QTY8 multiplied by the number of scalar
instructions - is going to get pretty mental, pretty fast.  still,
hey: omelette, eggs as they say.

predication is going to make it even more fun - here's one of the many
unit tests i added for SV-RV:
https://git.libre-soc.org/?p=riscv-tests.git;a=blob;f=isa/rv64ui/sv_addi_predicated_subvl.S;h=ea30797a70675e3fabd73ee66b7ee68d470aca58;hb=1a77df3e377db9675c8633fee70e2207f71d99be

on top of that, polymorphic elwidth overrides will also be needed:
https://git.libre-soc.org/?p=riscv-tests.git;a=blob;f=isa/rv64ui/sv_addw_elwidth.S;h=90ef5ca711ac6d3b81e0f61bf303683a85bc493a;hb=1a77df3e377db9675c8633fee70e2207f71d99be

the important thing is, here, we've a start, with this (slow)
simulator, and it's functional.

l.

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