[Libre-soc-dev] daily kan-ban update 24dec2021

[lkcl]

yesterday thanks to cesar fixing the DMI step bug i was able to do a side-by-side verilator comparison of microwatt and libresoc with mmu.bin

this identified that mmu lookup is not quite right, but also showed me that MSR.IR has to be obeyed: mmu.bin is executing with MSR.DR (data) set but IR (instruction relocation) off.

from the memory dumps of microwatt accessing the wishbone interface i should be able to recreate the contents of the RADIX pagetables and create a sim unit test.

working with verilator gtkwave traces is difficult because it strips the string details such as the FSM states and Function Unit etc.

l.