[Libre-soc-dev] LDST Exceptions [was: daily kan-ban update 02dec2021]

[Luke Kenneth Casson Leighton]

On Thu, Dec 2, 2021 at 7:00 PM Tobias Platen
<libre-soc at platen-software.de> wrote:

> today: thinking how to implement exception handling,

it's basically all done: everything is there.  it *should* just "work",
and if it doesn't then that's more a bug than requiring "implementation".


it's down in LDSTCompUnit [1]  exceptions are noted by the
exc_o.happened flag that comes from the LDSTException Record
 99 from soc.experiment.pimem import LDSTException

the exception comes from the PortInterface (which is the important
bit that you've been sorting out, without which none of what i am
about to describe will get triggered)

 539         comb += self.exc_o.eq(pi.exc_o)  # exception occurred

both terminate and canceln are set
 319         comb += terminate.eq(self.go_die_i | self.exc_o.happened)
 482         comb += canceln.eq(~self.exc_o.happened & self.shadown_i)

exceptions are amalgamated in core.py [2]

 259         for exc in self.fus.excs.values():
 260             el.append(exc.happened)
 261         if len(el) > 0: # at least one exception
 262             comb += self.o.exc_happened.eq(Cat(*el).bool())

(LDST *PROHIBITS* any other instructions from being executed after
it at the moment.  this avoids a need for speculative shadow-cancellation
logic)

issuer [3] then notes if the result of the operation caused an exception

 868                     with m.If(exc_happened):
 869                         sync +=
pdecode2.ldst_exc.eq(core.fus.get_exc("ldst0"))

does *NOT* request a new instruction but instead jumps directly
to the "Decode" phase

 878                         # return directly to Decode if Execute generated an
 879                         # exception.
 880                         with m.If(pdecode2.ldst_exc.happened):
 881                             m.next = "DECODE_SV"

and this REWRITES (overwrites) the instruction in PowerDecoder2 [4],
requesting a RE-INTERPRETATION of that instruction (ignoring
the actual instruction entirely) as an OP_TRAP instead of as an OP_LD.

1506         with m.If(ldst_exc.happened):
1507             with m.If(ldst_exc.alignment):
1508                 self.trap(m, TT.PRIV, 0x600)

that operation - now interpreted as an OP_TRAP - results in
the execution *of* a TRAP micro-op, where the TRAP pipeline [5]
has *already* been coded up to handle LDST memory instructions,
and already coded up to set the required SRR1 bits

 207                     with m.If(traptype & TT.MEMEXC):
 208                         # decode exception bits, store in SRR1
 209                         exc = LDSTException("trapexc")
 210                         comb += exc.eq(op.ldst_exc)
 211                         comb += srr1_o.data[PI.INVALID].eq(exc.invalid)
 212                         comb += srr1_o.data[PI.PERMERR].eq(exc.perm_error)
 213                         comb += srr1_o.data[PI.ILLEG].eq(exc.badtree)
 214                         comb += srr1_o.data[PI.PRIV].eq(exc.rc_error)

bottom line is: there should be nothing actually in need of actual
"implementation" here.  all the pieces of the puzzle are, strictly speaking,
in place.  it's just never been tested yet.

l.

[1]
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/experiment/compldst_multi.py;h=2baedc29f03cdb4a49431d9b69f21ee8cdd901bb;hb=9b49a17440aa1ae3422a57f5fc2dde51a66e32e4#l482

[2]
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/core.py;h=428b19f29bf5743b2a50b0d5e0a9652368d58636;hb=9b49a17440aa1ae3422a57f5fc2dde51a66e32e4#l262

[3]
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/simple/issuer.py;h=8b04ee0b0ccc7011577fe56b45b5de8c7954242d;hb=9b49a17440aa1ae3422a57f5fc2dde51a66e32e4#l858

[4]
https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/decoder/power_decoder2.py;h=44b1bf7d70725a1aaea8798facba65d34780506f;hb=8be0ddbea540a3e57af468f79838a740bc23eccf#l1504

[5]
https://git.libre-soc.org/?p=soc.git;a=blob;f=src/soc/fu/trap/main_stage.py;h=c597b75e7e01f57375ff20d2fd05cb1f6e8c686e;hb=9b49a17440aa1ae3422a57f5fc2dde51a66e32e4#l207