[Libre-soc-dev] L0 Cache Buffer

[Luke Kenneth Casson Leighton]

anton, hi, here is the page containing the diagram for what we called
the "L0 Cache Buffer"
https://libre-soc.org/3d_gpu/architecture/memory_and_cache/

we have a standard interface (a nmigen object / record) called "PortInterface"
which has all the usual signals: data, address, LD/ST request,
addr_ok, exception,
but where the length is specified as a per-byte "mask" per bit

this is processed by LDSTSplitter into *two* PortInterfaces, where the addresses
are now 8-byte aligned, and the non-aligned "masks" have been been split
across the two.

example:

LD 0x0003 8-bytes =>

* even port LD 0x0000 5-bit mask 0b11111000
* odd port LD 0x0008 3-bit mask 0b00000111

you can then take all the EVEN requests, separated from ODD requests, and
put all EVEN requests into the EVEN DataMerger, and all ODD requests
into the ODD DataMerger

then, because all of the requests comprise bit-level masks, you can merge
all of the bit-masks in the EVEN side, and (separately) merge all of the
bit-masks on the ODD side...

... this of course if they have the same MSBs in Addr[5:11] and Addr[12:48]...

and you can then pick one of them (PriorityPicker) on each side to pass
through to a left-side L1 Cache and a right-side L1 Cache.

or, other such scheme, making a 256-bit-wide single request etc. etc. etc.

but the primary focus here is on the address and data merging.

l.



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