[Libre-soc-dev] Introduction - Anton

[lkcl]

On August 24, 2021 10:01:09 PM UTC, Anton Lechanka <lechenko at bsuir.by> wrote:
>Hi All,
>
>My name is Anton Lechanka, I am a software engineer and assistant
>professor in Computer Architecture.

like jacib said, great to hear from you.

>I used to do some software simulation and microarchitecture tasks a
>few years ago.

interesting. you may be intrigued to know, we put in a new Grant request to use Peter Hsu's cavatools for the basis of a new Power ISA simulator.

>Now I would like to join your community and work on this fascinating
>project.
>I have read the charter and I agree to abide by it.

fantastic.  i'm assuming that you'd like to receive donations from NLnet, if so please do carry on through the checklist on the "how can i help as a developer" section, we use people's wiki homepage to track payments (example http://libre-soc.org/lkcl)

second, do send me an ssh public key i'll add you to the list.

third, you no doubt saw we use nmigen, this is because we have some Serious OO Design work to do, and the evaluation for all other HDL tools came up either short or so-short-you-need-a-microscope.

to illustrate, here's what can be done by using operator-overloading at the python level:
https://libre-soc.org/3d_gpu/architecture/dynamic_simd/

if you'd like to jump straight in, an immediate useful task would be binutils support for SVP64.  i am currently using a python class to generate ".long xxx; v3.0b asmop" and in some cases ".long xxx .long yyyy"

the bugreport is here:
https://bugs.libre-soc.org/show_bug.cgi?id=550

it will give you an immediate feel for the SVP64 format.

the only thing: it is *not* a good idea to hand-create the tables needed by binutils.  these should be *auto-generated*, teaching sv_analysis.py how to do that.

https://git.libre-soc.org/?p=openpower-isa.git;a=blob;f=src/openpower/sv/sv_analysis.py;hb=HEAD

there's nothing particularly sophisticated or clever about that program: it's written in a bland, non-OO "Get It Done" style.  it:
* reads OpenPOWER ISA v3.0B CSV files containing micro-code-style instruction format information
(exactly like the tables in binutils)
* identifies and groups v3.0B instructions by identical register file profile (number of Read regs, number of Write regs, number of CR regs read etc)
* assigns an SVP64 "Style" to each (Twin/Single-predicate, 2 or 3 EXTRA bits for reg extension)
* spits out *more* CSV files with that grouping information in it, to assist in decoding

thus rather than hand-create the SVP64 decoding information in binutils it should be trivial to autogenerate c header files and c structs.

this will give you a good running start directly into how SVP64 is formatted.

interested? :)

l.