[Libre-soc-dev] Arjun Nag

[Arjun Nag]

Hello everyone,
I am here with a quick intro...


• Design Verification Engineer in the field of VLSI
• Hands on Experience in System Verilog, Verilog & VHDL.
• Good Knowledge of UVM (Universal Verification Methodology).
• Good understanding of SoC level Test bench Architecture
• Good Hands-on at RTL - C Co simulation on HLS tool
• Well versed in creating the OVC’s and UVC’s
• Good understanding of Processor boot flows
• Good understanding of Verification flow at SoC level
• Good Knowledge of FPGA, ASIC & SoC Design & Verification Life Cycles.
• Excellent understanding of protocols like PCIe (Gen 2 & 3), UART, SPI and
Compression/decompression Engine, QSPI,  AMBA AXI, SMB & HTP
• Good Knowledge in both functional and gate level simulations.
• Possess hands on experience in Emulating complex SoC designs, Interface
Build-up and Debugging.
• Good understanding of Design Partitioning and Trimming.
• Hands-on Working experience of Mentor Veloce Quattro 2 & MAXIMUS
Emulators.
• Mentor Veloce Quattro 2 based Emulation setup and chip compile/run hands
on experience
• Experience in Emulating Complex memory controllers and functional IP
blocks in In Circuit Emulation (ICE) and TBX Modes.
• Good understanding of differences between RTL and X-RTL.
• Well versed in setting up software top and hardware top in a Top Level
Emulation test bench.
• Have good knowledge on protocols like PCIe Gen 2, UART, SPI and
Compression/decompression Engine.
• Excellent debugging skills
• Excellent Documentation skills
• Knowledge of Configuration Management tools like Tele logic DOORS and CM
Synergy tools.
• Fair Knowledge of IBM rational Tools like Clear Case and Clear Quest
• Familiar with concepts of C Language and Object Oriented Methodology.
• Willing to learn new skills and ability to learn fast.
• Technical support to team members