[Libre-soc-dev] [RFC] SVP64 on branch instructions

[Luke Kenneth Casson Leighton]

drat. fricking gmail HTML Basic mode is barely useable. hit send
instead of save. grrr.

ok.

https://libre-soc.org/openpower/sv/branches/?updated

i've added the example and created SVP64 hypothetical assembler.

i very deliberately placed the calculation of ANDing the predicate
with the CR just before each call to f() and g(). the CR Vector
*BEFORE* bring transferred to r30 is used, there, because it is a pain
to cross-interact integers with Vector CRs.

one of the tests (the else.any) is deliberately inverted: mask=~r30

this is to illustrate how and what SNZ immediate field is for.

ANDing of all tests is still done, but instead of sz (source zero in
masked out bits) a **ONE** is put in the place of the CR Field
element, **NOT** a zero.

this causes the ANDing to effectively IGNORE masked-out bits but still
keep decrementing CTR (if the relevant CTR bit is set).

thus, CTR branch conditional mode *still operates correctly* counting
down the total number of elements in an array, even when sone elements
of that array should be masked out.

where you do not want that behaviour, instead wanting CTR to count
down ONLY mask-selected elements, you would not use sz.  this woukd
skip both the element test *and* skip CTR decrementing.

what _would_ be nice is if bc were to update the CR field based on the mask.

however to be absolutely honest i think this is too much, and it needs
to be optional, and unfortunately we are out of bits.

l.