[Libre-soc-dev] Fwd: soclayout problem

[lkcl]

On Tue, Apr 27, 2021 at 5:05 PM Staf Verhaegen <staf at fibraservi.eu> wrote:
>
>
> Problems seems to be that the memory is not defined as blackbox in
> spblock512w64b8w_n.v

right.  after adding "blackbox", although the BLIF creation succeeded,
the Hurricane import FAILED.

so i went back and looked at the dummy PLL....

On di, 2021-04-27 at 17:42 +0200, Jean-Paul Chaput wrote:

>   One more problem : even if it is flagged as a blackbox, the blif
>   file will contains a description of the spblock512w64b8w_0.v
>   telling that "d == q" :

... and YES, the dummy PLL *ALSO* has "fake signals" in it.

i have now been through all permutations:

* with blackbox=1
* without d==q (and without dummy PLL "fake" signals)

in each case there are DIFFERENT yosys interactions, all of which
cause, in 100% of cases, a failure of some kind.

what we want to achieve is not going to be possible without using
another approach.

my feeling is that an actual library (like LibreSOCIO) containing
actual cells (spblock51264b8w, pll) is what is going to work, here.
looking at this:
https://gitlab.com/Chips4Makers/c4m-pdk-freepdk45/-/blob/released-libresoc/coriolis/techno/etc/coriolis2/NDA/node45/freepdk45_c4m/LibreSOCIO.py

i do not believe it would actually be difficult to do.

i will give this a try, today.  any objections or roadblocks or "yew
dont wanna dew thaaat" or "yep that's not gonna work", please do say
soon

l.