[Libre-soc-dev] soclayout problem

[Staf Verhaegen]

On di, 2021-04-27 at 15:44 +0100, Luke Kenneth Casson Leighton wrote:
> On Tue, Apr 27, 2021 at 3:31 PM Staf Verhaegen <staf at fibraservi.eu>
> wrote:
> > You see that the io module is used in .subckt but has no model
> > section.
> 
> that - no model being present - is exactly what the problem is.
> if you only have one instance (one PLL, or one spblock512w64b8w),
> thenthe model *does* get copied into the BLIF file (even when marked
> as ablackbox)

I cannot reproduce that yosys does write model section for single
blackbox instance. I therefor assume that your PLL is not really a
blackbox model.
In yosys
% read_verilog single.v
% write_blif single.blif

single.v:
> (* blackbox = 1 *)
> module io(in, out);
> input in;
> output out;
> 
> endmodule
> 
> 
> module single(in, out);
> input in;
> output out;
> 
> io io1(in, out);
> 
> endmodule 

single.blif:
> # Generated by Yosys 0.9+4052 (git sha1 4c21eab27, gcc 9.3.0-
> 17ubuntu1~20.04 -fPIC -Os)
> 
> .model single
> .inputs in
> .outputs out
> .names $false
> .names $true
> 1
> .names $undef
> .subckt io $1=in $2=out
> .end

Staf.