[Libre-soc-dev] VERSA_ECP5 JTAG TAP interface confirmed functional

[Luke Kenneth Casson Leighton]

JSharpe of #talos-workstation on freenode is going to look at a quote for
us to assemble LFE5G 85k ulx3s with 128 mbyte (1 gbit) SDRAM ICs.
https://bugs.libre-soc.org/show_bug.cgi?id=633


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crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68


On Mon, Apr 26, 2021 at 4:24 PM Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

> https://github.com/emard/ulx3s
>
> that's an open design.
>
>
> https://www.digikey.co.uk/product-detail/en/alliance-memory-inc/AS4C64M16D1-6TCN/1450-1332-ND/5797372
>
> found a compatible (TSSOP-66) ASIC with 128 megabytes of RAM.  which is
> probably good enough.
>
> l.
>
>