[Libre-soc-dev] Update on Coriolis & LS180.

[Staf Verhaegen]

On ma, 2021-04-26 at 16:05 +0200, Jean-Paul Chaput wrote:
> 
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>     Either we go symbolic and can use cougar/lvx or we go real  and
> for the lack of a public extractor you will not be able  to perform
> the post-layout verification.

There are different types of post-layout verification:
one of them is to see if the changes made to the netlist by high fan-
out net and clock-tree synthesis did not change functionality. This can
be checked by simulating the netlist after these steps and doing LVS
between this netlist and the layout. So no parasitic extraction is
needed.
Other type is verify timing closure, there one need parasitics if one
wants to verify max. operating frequency. This is nice to have but not
strictly necessary for this tape-out. For hold violations the netlist
without parasitics is the worst case.
>     But what we needed was you to supply us with patterns and  cocotb
> setup so that we have a "validation" check.    The whole point being
> that pre-P&R and post-P&R must behave  exactly the same. Basically
> the P&R only insert buffers and  diodes. So any problem in post-P&R
> (which isn't already present  in the pre-P&R) would be for me to
> solve.

The cocotb setup has been done in git repo soc-cocotb-sim:
https://git.libre-soc.org/?p=soc-cocotb-sim.git

greets,
Staf.