[Libre-soc-dev] ls180 update

[Luke Kenneth Casson Leighton]

On Friday, April 16, 2021, Luke Kenneth Casson Leighton <lkcl at lkcl.net>
wrote:

>
> * i have been doing JTAG ghdl cocotb simulations of pre and post layout,
> with a small test, this created a series of errors which Jean-Paul has
> fixed.  the post pnr wishbone test takes several seconds to complete: it
> will be quite fascinating (scary) to run the full ls180.
>

as an experiment i extracted the vhdl using yosys, into a verilog file for
compilation with verilator, which is over 1,000,000 lines long.

from that 1,000,000 line file verilator has produced 3,000 sub-files.
compiling even the ones with a #include and nothing else takes 10 minutes
each.  estimates for completion of compilation is therefore several weeks.

this is not reasonable unless we have access to a beowulf cluster with
distcc.

l.



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