[Libre-soc-dev] cxxsim with jtag connections

[Luke Kenneth Casson Leighton]

cxxsim turns out to be an ubiquitous, reliable and effective way to
simulate ls180 in all stages of transformation from nmigen, to verilog, to
VHDL pre and post routing.

the idea is:

* simulate the design and connect with jtag
* take the BLIF file, turn it into VHDL, simulate that and connect with jtag
* create the routing, extract the netlist as VHDL, do the same
* compile for the ECP5, run the exact same JTAG tests
* get the ASIC back, run the exact same JTAG tests.

key to that is the following:
https://git.libre-soc.org/?p=soc-cxxrtl-sim.git;a=blob;f=ls180_test/main.cpp;h=c46e4d1c8b8eea87e2d0d61b679d9f4e8c85527a;hb=5befb17024c58d726b29e033aa1b54c44fc945e2#l121

right *in the middle* of the cxxsim is an openocd jtagremote bitbanging
socket which can be connected to with the openocd remote_bitbang interface.

for the actual ASIC and ECP5 a different openocd initialisation file can be
used.  it is near trivial.

the extremely nice thing about cxxsim is that it doesn't care in the least
whether the input language is verilog, vhdl or ilang, it is all treated the
same.  for the coriolis2 simulations part of the input is the actual cell
libraries themselves.

though gate-level simulation it is possible to ensure that at every stage
of transformation the ASIC netlist remains "undamaged".

we therefore stand a reasonable chance of getting a working ASIC back.

l.




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