[Libre-soc-dev] svp64 questions: variable parallelism vs predictability

[Alexandre Oliva]

Should I raise them here, or in bugzilla (213?)

One issue in my mind is parallelism and ordering guarantees of the
specification, considering that the amount of parallelism may vary.
Consider:

  setvli 45  ; set vector length to 45
  mv 39, 36  ; copy 45 registers from r36 on to r39 on

Must this overwrite r40 with r37 before copying it to r43?
Or must it load r40 before overwriting it, even at high parallelism?
Or must it lower parallelism to avoid such overwrites?
Or can it vary depending on the amount of parallelism?

-- 
Alexandre Oliva, happy hacker  https://FSFLA.org/blogs/lxo/
   Free Software Activist         GNU Toolchain Engineer
        Vim, Vi, Voltei pro Emacs -- GNUlius Caesar