[Libre-soc-dev] svp64

[Luke Kenneth Casson Leighton]

On Friday, December 18, 2020, Jacob Lifshay <programmerjake at gmail.com>
wrote:
> On Fri, Dec 18, 2020, 15:35 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>> * still do not know what the best arrangement for CRs is.
>>
>
> I'm for the arrangement that mirrors the register layout I picked for
> FP/Int registers.


CR[i] is the notation used by the OpenPower spec to refer to CR field #i,
so FP instructions with Rc=1 write to CR[1] aka SVCR1_000.


so when vectorisation is enabled CR[2] and onwards are destroyed.  this
means that every vector operation requires callee saving of CRs.

it would be much more sensible to start from say CR[8] for INT operations
and say from CR[32] for FP (debatable).

deliberately in increments of 8 so that the hardware is kept simple for the
DMs.

the concept of compatibility with a SIMD system designed in 1998 needs to
be expunged :)

however when a given reg result is marked as scalar we need to have
compatibility with v.3.0B/1B so that an extra mv is not required plus there
are no "surprises".

in other words the exact same algorithm for reg naming that you came up
with 18 months ago.

i'm going to remove the new naming and replace it with the simole concept,
"regs are extended linearly". CR0.. CR63, r0..r127

this is understandable.

in 5 years when we have time and funding extending to 256 regs can be
investigated.

l






-- 
---
crowd-funded eco-conscious hardware: https://www.crowdsupply.com/eoma68