[Libre-soc-dev] v3.1B prefix

[Luke Kenneth Casson Leighton]

On 12/14/20, Alexandre Oliva <oliva at gnu.org> wrote:
> On Dec  8, 2020, Alexandre Oliva <oliva at gnu.org> wrote:
>
>> On Dec  7, 2020, Luke Kenneth Casson Leighton <lkcl at lkcl.net> wrote:
>>> i did find it odd that there's no 16-bit imm instructions,
>
>> Sorry, I failed to mention that they're not implemented yet.
>
> Now they are.  I'm pretty sure the immediates for addi and addis are not
> implemented according to the best use we could make of them, but the
> shifts are as described in the specs.

brilliant.

> I've also implemented conditinal register opcodes, system opcodes,
> 16-imm loads, stores, shifts, and compares; I put in code to parse
> condition bit expressions and implemented bc[l] (16-imm) and bclr[l]
> (10- and 16-bit).

ah cool!

so, how did it come out? is it making sense and bringing numbers down
to anything approaching "compelling"?

l.