[Libre-soc-dev] fantastically-weird regfile

[Cole Poirier]

On Sunday, December 13, 2020, Jacob Lifshay <programmerjake at gmail.com>
wrote:

> On Sun, Dec 13, 2020, 16:12 Luke Kenneth Casson Leighton <lkcl at lkcl.net>
> wrote:
>
> > i had an idea about the CR regfile when it's vectorised.  this is one
> > of the oddest designs but there is a reason for it. see
> > https://libre-soc.org/openpower/sv/svp_rewrite/svp64/discussion/ for
> > full details
> >
> > the issue we've got is that scalar CRs were not intended to be
> > vectorised.  so in scalar OpenPOWER there's only 8 of them.  they're
> > "dedicated": CR0 is for INT/Logical, CR1 for FP, CR6 for SIMD VSX.
> >
> > so here's the problem when we apply SV, which normally applies
> > "sequential" increments: any SV-Vectorised Rc=1 INT operation is
> > *automatically* going to wipe out CR1.
> >
> > what if, then, the numbering went:
> >
> >     0 8 16 24 32 40 48 56
> >     1 9 17 ....
> >
> > that way it would only be vector INT operations longer than 8 that
> > would destroy CR1.
> >
> > that in turn would imply that the CRs would be treated as an 8x8
> > matrix, dual-ported, reading horizontally *and vertically*!  which is
> > just so spectacularly weird i feel it has merit just for fits and
> > giggles.
> >
>
> That's very similar to what I already did for int and fp registers, see:
>
> https://libre-soc.org/openpower/sv/svp_rewrite/svp64/
>

I like it a lot. Would this help with port contention? I also like it as it
very much reminds me of the dependency matrices.

Cole