[Libre-soc-dev] Some high-level information about Apple's new M1 SoCs

[Luke Kenneth Casson Leighton]

On 12/11/20, Jacob Lifshay <programmerjake at gmail.com> wrote:

> IIRC we had talked previously about building a 8-wide processor too, but we
> decided we're putting that off till later since we wanted to get a working
> processor first, then we'll have a better opportunity to go all out once we
> demonstrated that we can make something that works.

i asked pangelo to post this after he raised it on irc because we had
just had a discussion in which you created a carry-lookahead style O(n
log n) multi-issue instruction length identifier.

i was both fascinated and horrified to see that x86 multi issue decode
has to start decoding instructions from *random byte locations* in the
desperate hope that, half way through that, some of them will go "ah!
yippeee! i know the length of this instruction! all youse f*****rs can
stop wasting power now"

if they don't do that, instead waiting until the 1st op is fully
decoded, the length of time it takes is so high that the chances of
doing multi-issue are absolute zero.

by contrast the relative simplicity of ARM (and OpenPOWER) allow a
near-trivial length-detection and consequently 8-issue is perfectly
reasonable.

absolute monstrous Dependency Matrices, vast regfile porting, insane
crossbar widths and a THOUSAND in-flight instructions are the result,
but hey!

l.